Tuning the Pentium Pro microarchitecture

in tel Corporation %is inside look at a large microprocessor development project reveals some of the reasoning vor goals, changes, trade-osfsi andJerformance simulation) that lay behind itsjnal form. esigning a wholly new microprocessor is dfficult and expensive. To jus-D tlfy this effort, a major new microarchitecture must improve performance one and a half or two times over the previous generation microarchitecture, when evaluated on equivalent process technology. In addition, semiconductor process technology continues to evolve while the processor design is in progress. The previous-generation microarchitecture increases in clock speed and performance due to compactions and conversion to newer technology. A new microarchitecture must " intercept " the process technology to achieve a compounding of process and microarchitectural speedups. The process technology, degree of pipelining, and amount of effort a team is willing to spend on circuit and layout issues determine the clock speed of a microarchi-tecture. Typically, a mlcroarchitecture will start with the same clock speed as a prior microarchitecture (adjusted for process technology scaling). This enables the maximum reuse of past designs and circuits, and fits the new design to the existing product development tools and methodology. Performance enhancements should come primarily from the microarchitecture and not from clock speed enhancements per se. Often, a new processor's die area is close to the maximum that can be manufactured. This design choice stems from marketplace competitiveness and efforts to get as much performance as possible in the new microar-chitecture. While making the die smaller and cheaper and improving performance are desirable, it is generally not possible to achieve a 1.5-to-2-times-better performance goal without using at least 1.5 to 2 times a prior design's transistors. Finally, new processor designs often incorporate new features. As the performance of the core logic improves, designs must continue to enhance the bus and cache architecture to keep pace with the core Further, as other technologies (such as mul-tiprocessing) mature, there is a natural tendency to draw them into the processor design as a way of providing additional features and value for the end user The large installed base and broad range of applications for the Intel architecture place additional constraints on the design, constraints beyond the purely academic ones of performance and clock frequency We do not have the flexibility to control software applications, compilers, or operating systems in the same way system vendors can We cannot remove obsolete features and must cater to a …